Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 10 Issue 2, May 2013

Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints
Angeliki Kritikakou, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, Costas Goutis
Article No.: 6
DOI: 10.1145/2459316.2459317

A systematic methodology for near-optimal software/hardware codesign mapping onto an FPGA platform with microprocessor and HW accelerators is proposed. The mapping steps deal with the inter-organization, the foreground memory management, and the...

Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory
Lei Jiang, Yu Du, Bo Zhao, Youtao Zhang, Bruce R. Childers, Jun Yang
Article No.: 7
DOI: 10.1145/2459316.2459318

Phase Change Memory (PCM) has recently emerged as a promising memory technology. However, PCM’s limited write endurance restricts its immediate use as a replacement for DRAM. To extend the lifetime of PCM chips, wear-leveling and salvaging...

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA
Kyuseung Han, Junwhan Ahn, Kiyoung Choi
Article No.: 8
DOI: 10.1145/2459316.2459319

Coarse-grained reconfigurable architecture typically has an array of processing elements which are controlled by a centralized unit. This makes it difficult to execute programs having control divergence among PEs without predication. However,...

MP-Tomasulo: A Dependency-Aware Automatic Parallel Execution Engine for Sequential Programs
Chao Wang, Xi Li, Junneng Zhang, Xuehai Zhou, Xiaoning Nie
Article No.: 9
DOI: 10.1145/2459316.2459320

This article presents MP-Tomasulo, a dependency-aware automatic parallel task execution engine for sequential programs. Applying the instruction-level Tomasulo algorithm to MPSoC environments, MP-Tomasulo detects and eliminates Write-After-Write...