Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 9 Issue 1, March 2012

Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value Prediction
Walid J. Ghandour, Haitham Akkary, Wes Masri
Article No.: 1
DOI: 10.1145/2133382.2133383

Value prediction is a technique to increase parallelism by attempting to overcome serialization constraints caused by true data dependences. By predicting the outcome of an instruction before it executes, value prediction allows data...

When Prefetching Works, When It Doesn’t, and Why
Jaekyu Lee, Hyesoon Kim, Richard Vuduc
Article No.: 2
DOI: 10.1145/2133382.2133384

In emerging and future high-end processor systems, tolerating increasing cache miss latency and properly managing memory bandwidth will be critical to achieving high performance. Prefetching, in both hardware and software, is among our most...

Dataflow Tomography: Information Flow Tracking For Understanding and Visualizing Full Systems
Bita Mazloom, Shashidhar Mysore, Mohit Tiwari, Banit Agrawal, Tim Sherwood
Article No.: 3
DOI: 10.1145/2133382.2133385

It is not uncommon for modern systems to be composed of a variety of interacting services, running across multiple machines in such a way that most developers do not really understand the whole system. As abstraction is layered atop abstraction,...

Improving System Energy Efficiency with Memory Rank Subsetting
Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber
Article No.: 4
DOI: 10.1145/2133382.2133386

VLSI process technology scaling has enabled dramatic improvements in the capacity and peak bandwidth of DRAM devices. However, current standard DDRx DIMM memory interfaces are not well tailored to achieve high energy efficiency and...

Comparability Graph Coloring for Optimizing Utilization of Software-Managed Stream Register Files for Stream Processors
Xuejun Yang, Li Wang, Jingling Xue, Qingbo Wu
Article No.: 5
DOI: 10.1145/2133382.2133387

The stream processors represent a promising alternative to traditional cache-based general-purpose processors in achieving high performance in stream applications (media and some scientific applications). In a stream programming model for stream...

A Massively Parallel, Energy Efficient Programmable Accelerator for Learning and Classification
Abhinandan Majumdar, Srihari Cadambi, Michela Becchi, Srimat T. Chakradhar, Hans Peter Graf
Article No.: 6
DOI: 10.1145/2133382.2133388

Applications that use learning and classification algorithms operate on large amounts of unstructured data, and have stringent performance constraints. For such applications, the performance of general purpose processors scales poorly with data...