Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 7 Issue 2, September 2010

Token tenure and PATCH: A predictive/adaptive token-counting hybrid
Arun Raghavan, Colin Blundell, Milo M. K. Martin
Article No.: 6
DOI: 10.1145/1839667.1839668

Traditional coherence protocols present a set of difficult trade-offs: the reliance of snoopy protocols on broadcast and ordered interconnects limits their scalability, while directory protocols incur a performance penalty on sharing misses due to...

Automatic feedback-directed object fusing
Christian Wimmer, Hanspeter Mössenbösck
Article No.: 7
DOI: 10.1145/1839667.1839669

Object fusing is an optimization that embeds certain referenced objects into their referencing object. The order of objects on the heap is changed in such a way that objects that are accessed together are placed next to each other in memory. Their...

Applied inference: Case studies in microarchitectural design
Benjamin C. Lee, David Brooks
Article No.: 8
DOI: 10.1145/1839667.1839670

We propose and apply a new simulation paradigm for microarchitectural design evaluation and optimization. This paradigm enables more comprehensive design studies by combining spatial sampling and statistical inference. Specifically, this paradigm...

Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors
R. Rakvic, Q. Cai, J. González, G. Magklis, P. Chaparro, A. González
Article No.: 9
DOI: 10.1145/1839667.1839671

We provide an analysis of thread-management techniques that increase performance or reduce energy in multicore and Simultaneous Multithreaded (SMT) cores. Thread delaying reduces energy consumption by running the core containing the critical...

A memory-efficient pipelined implementation of the aho-corasick string-matching algorithm
Derek Pao, Wei Lin, Bin Liu
Article No.: 10
DOI: 10.1145/1839667.1839672

With rapid advancement in Internet technology and usages, some emerging applications in data communications and network security require matching of huge volume of data against large signature sets with thousands of strings in real time. In this...

Exploiting the reuse supplied by loop-dependent stream references for stream processors
Xuejun Yang, Ying Zhang, Xicheng Lu, Jingling Xue, Ian Rogers, Gen Li, Guibin Wang, Xudong Fang
Article No.: 11
DOI: 10.1145/1839667.1839673

Memory accesses limit the performance of stream processors. By exploiting the reuse of data held in the Stream Register File (SRF), an on-chip, software controlled storage, the number of memory accesses can be reduced. In current stream compilers,...

Eliminating voltage emergencies via software-guided code transformations
Vijay Janapa Reddi, Simone Campanoni, Meeta S. Gupta, Michael D. Smith, Gu-Yeon Wei, David Brooks, Kim Hazelwood
Article No.: 12
DOI: 10.1145/1839667.1839674

In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor supply voltage fluctuations....