Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 7 Issue 1, April 2010

A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu
Article No.: 1
DOI: 10.1145/1736065.1736066

In this article, we investigate the Intellectual Property (IP) mapping problem that maps a given set of IP cores onto the tiles of a mesh-based Network-on-Chip (NoC) architecture such that the power consumption due to intercore communications is...

A hardware/software framework for instruction and data scratchpad memory allocation
Zhong-Ho Chen, Alvin W. Y. Su
Article No.: 2
DOI: 10.1145/1736065.1736067

Previous researches show that a scratchpad memory device consumed less energy than a cache device with the same capacity. In this article, we locate the scratchpad memory (SPM) in the top level of the memory hierarchy to reduce the energy...

Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching
Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Hsien-Hsin S. Lee
Article No.: 3
DOI: 10.1145/1736065.1736068

Heterogeneous multicore processors have emerged as an energy- and area-efficient architectural solution to improving performance for domain-specific applications such as those with a plethora of data-level parallelism. These processors typically...

An analysis of on-chip interconnection networks for large-scale chip multiprocessors
Daniel Sanchez, George Michelogiannakis, Christos Kozyrakis
Article No.: 4
DOI: 10.1145/1756065.1736069

With the number of cores of chip multiprocessors (CMPs) rapidly growing as technology scales down, connecting the different components of a CMP in a scalable and efficient way becomes increasingly challenging. In this article, we explore the...

Performance-aware thermal management via task scheduling
Xiuyi Zhou, Jun Yang, Marek Chrobak, Youtao Zhang
Article No.: 5
DOI: 10.1145/1736065.1736070

High on-chip temperature impairs the processor's reliability and reduces its lifetime. Hardware-level dynamic thermal management (DTM) techniques can effectively constrain the chip temperature, but degrades the performance. We propose an OS-level...