Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 6 Issue 3, September 2009

Compiler-directed scratchpad memory management via graph coloring
Lian Li, Hui Feng, Jingling Xue
Article No.: 9
DOI: 10.1145/1582710.1582711

Scratchpad memory (SPM), a fast on-chip SRAM managed by software, is widely used in embedded systems. This article introduces a general-purpose compiler approach, called memory coloring, to assign static data aggregates, such as arrays and...

Checkpoint allocation and release
Amit Golander, Shlomo Weiss
Article No.: 10
DOI: 10.1145/1582710.1582712

Out-of-order speculative processors need a bookkeeping method to recover from incorrect speculation. In recent years, several microarchitectures that employ checkpoints have been proposed, either extending the reorder buffer or entirely replacing...

Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors
Weifeng Xu, Russell Tessier
Article No.: 11
DOI: 10.1145/1582710.1582713

As technology has advanced, the application space of Very Long Instruction Word (VLIW) processors has grown to include a variety of embedded platforms. Due to cost and power consumption constraints, many embedded VLIW processors contain limited...

Exploring the limits of early register release: Exploiting compiler analysis
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oğuz Ergin
Article No.: 12
DOI: 10.1145/1582710.1582714

Register pressure in modern superscalar processors can be reduced by releasing registers early and by copying their contents to cheap back-up storage. This article quantifies the potential benefits of register occupancy reduction and shows that...