Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 6 Issue 2, June 2009

MemTracker: An accelerator for memory debugging and monitoring
Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic
Article No.: 5
DOI: 10.1145/1543753.1543754

Memory bugs are a broad class of bugs that is becoming increasingly common with increasing software complexity, and many of these bugs are also security vulnerabilities. Existing software and hardware approaches for finding and identifying memory...

Service level agreement for multithreaded processors
Ron Gabor, Avi Mendelson, Shlomo Weiss
Article No.: 6
DOI: 10.1145/1543753.1543755

Multithreading is widely used to increase processor throughput. As the number of shared resources increase, managing them while guaranteeing predicted performance becomes a major problem. Attempts have been made in previous work to ease this via...

Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware
Wilson W. L. Fung, Ivan Sham, George Yuan, Tor M. Aamodt
Article No.: 7
DOI: 10.1145/1543753.1543756

Recent advances in graphics processing units (GPUs) have resulted in massively parallel hardware that is easily programmable and widely available in today's desktop and notebook computer systems. GPUs typically use single-instruction,...

Tolerating process variations in large, set-associative caches: The buddy cache
Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li
Article No.: 8
DOI: 10.1145/1543753.1543757

One important trend in today's microprocessor architectures is the increase in size of the processor caches. These caches also tend to be set associative. As technology scales, process variations are expected to increase the fault rates of the...