Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 5 Issue 3, November 2008

Comparative evaluation of memory models for chip multiprocessors
Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis
Article No.: 12
DOI: 10.1145/1455650.1455651

There are two competing models for the on-chip memory in Chip Multiprocessor (CMP) systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison of the two models under the...

Reducing register pressure in SMT processors through L2-miss-driven early register release
Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev
Article No.: 13
DOI: 10.1145/1455650.1455652

The register file is one of the most critical datapath components limiting the number of threads that can be supported on a simultaneous multithreading (SMT) processor. To allow the use of smaller register files without degrading performance,...

Exploiting selective placement for low-cost memory protection
Mojtaba Mehrara, Todd Austin
Article No.: 14
DOI: 10.1145/1455650.1455653

Many embedded processing applications, such as those found in the automotive or medical field, require hardware designs that are at the same time low cost and reliable. Traditionally, reliable memory systems have been implemented using coded...

Speculative return address stack management revisited
Hans Vandierendonck, André Seznec
Article No.: 15
DOI: 10.1145/1455650.1455654

Branch prediction feeds a speculative execution processor core with instructions. Branch mispredictions are inevitable and have negative effects on performance and energy consumption. With the advent of highly accurate conditional branch...