Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 5 Issue 1, May 2008

Brad Calder, Dean Tullsen
Article No.: 1
DOI: 10.1145/1369396.1369397

Formulating and implementing profiling over adaptive ranges
Shashidhar Mysore, Banit Agrawal, Rodolfo Neuber, Timothy Sherwood, Nisheeth Shrivastava, Subhash Suri
Article No.: 2
DOI: 10.1145/1369396.1369398

Modern computer systems are called on to deal with billions of events every second, whether they are executed instructions, accessed memory locations, or forwarded packets. This presents a serious challenge to those who seek to quantify, analyze,...

Compiler and hardware support for reducing the synchronization of speculative threads
Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan, Todd C. Mowry
Article No.: 3
DOI: 10.1145/1369396.1369399

Thread-level speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. In this article, we focus on one important limitation of program...

Addressing thermal nonuniformity in SMT workloads
Jonathan A. Winter, David H. Albonesi
Article No.: 4
DOI: 10.1145/1369396.1369400

We explore DTM techniques within the context of uniform and nonuniform SMT workloads. While DVS is suitable for addressing workloads with uniformly high temperatures, for nonuniform workloads, performance loss occurs because of the slowdown of the...

Versatility of extended subwords and the matrix register file
Asadollah Shahbahrami, Ben Juurlink, Stamatis Vassiliadis
Article No.: 5
DOI: 10.1145/1369396.1369401

Extended subwords and the matrix register file (MRF) are two micro architectural techniques that address some of the limitations of existing SIMD architectures. Extended subwords are wider than the data stored in memory. Specifically, for every...

Efficient hardware code generation for FPGAs
Zhi Guo, Walid Najjar, Betul Buyukkurt
Article No.: 6
DOI: 10.1145/1369396.1369402

The wider acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach in ROCCC. The smart buffer is a component that reuses input...

Design of the Java HotSpot™ client compiler for Java 6
Thomas Kotzmann, Christian Wimmer, Hanspeter Mössenböck, Thomas Rodriguez, Kenneth Russell, David Cox
Article No.: 7
DOI: 10.1145/1369396.1370017

Version 6 of Sun Microsystems' Java HotSpot™ VM ships with a redesigned version of the client just-in-time compiler that includes several research results of the last years. The client compiler is at the heart of the VM configuration used by...