Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 4 Issue 4, January 2008

Efficient architectural design space exploration via predictive modeling
Engin Ipek, Sally A. McKee, Karan Singh, Rich Caruana, Bronis R. de Supinski, Martin Schulz
Article No.: 1
DOI: 10.1145/1328195.1328196

Efficiently exploring exponential-size architectural design spaces with many interacting parameters remains an open problem: the sheer number of experiments required renders detailed simulation intractable. We attack this via an automated approach...

Virtual machine showdown: Stack versus registers
Yunhe Shi, Kevin Casey, M. Anton Ertl, David Gregg
Article No.: 2
DOI: 10.1145/1328195.1328197

Virtual machines (VMs) enable the distribution of programs in an architecture-neutral format, which can easily be interpreted or compiled. A long-running question in the design of VMs is whether a stack architecture or register architecture can be...

Exploiting virtual registers to reduce pressure on real registers
Jun Yan, Wei Zhang
Article No.: 3
DOI: 10.1145/1328195.1328198

It is well known that a large fraction of variables are short-lived. This paper proposes a novel approach to exploiting this fact to reduce the register pressure for pipelined processors with data-forwarding network. The idea is that the compiler...

Object co-location and memory reuse for Java programs
Zoe C. H. Yu, Francis C. M. Lau, Cho-Li Wang
Article No.: 4
DOI: 10.1145/1328195.1328199

We introduce a new memory management system, STEMA, which can improve the execution time of Java programs. STEMA detects prolific types on-the-fly and co-locates their objects in a special memory space which supports reuse of memory. We argue and...

Reducing cache misses through programmable decoders
Chuanjun Zhang
Article No.: 5
DOI: 10.1145/1328195.1328200

Level-one caches normally reside on a processor's critical path, which determines clock frequency. Therefore, fast access to level-one cache is important. Direct-mapped caches exhibit faster access time, but poor hit rates, compared with same...

Hiding the misprediction penalty of a resource-efficient high-performance processor
Amit Golander, Shlomo Weiss
Article No.: 6
DOI: 10.1145/1328195.1328201

Misprediction is a major obstacle for increasing speculative out-of-order processors performance. Performance degradation depends on both the number of misprediction events and the recovery time associated with each one of them. In recent years a...