Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 4 Issue 1, March 2007

Brad Calder, Dean Tullsen
Article No.: 1
DOI: 10.1145/1216544.1229348

Architecting a reliable CMP switch architecture
Kypros Constantinides, Stephen Plaza, Jason Blome, Valeria Bertacco, Scott Mahlke, Todd Austin, Bin Zhang, Michael Orshansky
Article No.: 2
DOI: 10.1145/1216544.1216545

As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transient errors, and transistor wear-out. Unless these challenges are...

ALP: Efficient support for all levels of parallelism for complex media applications
Ruchira Sasanka, Man-Lap Li, Sarita V. Adve, Yen-Kuang Chen, Eric Debes
Article No.: 3
DOI: 10.1145/1216544.1216546

The real-time execution of contemporary complex media applications requires energy-efficient processing capabilities beyond those of current superscalar processors. We observe that the complexity of contemporary media applications requires support...

Conserving network processor power consumption by exploiting traffic variability
Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
Article No.: 4
DOI: 10.1145/1216544.1216547

Network processors (NPs) have emerged as successful platforms for providing both high performance and flexibility in building powerful routers. Typical NPs incorporate multiprocessing and multithreading to achieve maximum parallel processing...

Software-directed power-aware interconnection networks
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
Article No.: 5
DOI: 10.1145/1216544.1216548

Interconnection networks have been deployed as the communication fabric in a wide spectrum of parallel computer systems, ranging from chip multiprocessors (CMPs) and embedded multicore systems-on-a-chip (SoCs) to clusters and server blades. Recent...

Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties
Yuan-Shin Hwang, Jia-Jhe Li
Article No.: 6
DOI: 10.1145/1216544.1216549

As transistors keep shrinking and on-chip caches keep growing, static power dissipation resulting from leakage of caches takes an increasing fraction of total power in processors. Several techniques have already been proposed to reduce leakage...

Single-dimension software pipelining for multidimensional loops
Hongbo Rong, Zhizhong Tang, R. Govindarajan, Alban Douillet, Guang R. Gao
Article No.: 7
DOI: 10.1145/1216544.1216550

Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to outer loops. This paper proposes a three-step approach, called single-dimension software pipelining (SSP), to...