Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 2 Issue 1, March 2005

Brad Calder, Dean Tullsen
Pages: 1-2
DOI: 10.1145/1061267.1061268

Efficient and flexible architectural support for dynamic monitoring
Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, Josep Torrellas
Pages: 3-33
DOI: 10.1145/1061267.1061269
Recent impressive performance improvements in computer architecture have not led to significant gains in the case of debugging. Software debugging often relies on inserting run-time software checks. In many cases, however, it is hard to find the root...

A way-halting cache for low-energy high-performance systems
Chuanjun Zhang, Frank Vahid, Jun Yang, Walid Najjar
Pages: 34-54
DOI: 10.1145/1061267.1061270
Caches contribute to much of a microprocessor system's power and energy consumption. Numerous new cache architectures, such as phased, pseudo-set-associative, way predicting, reactive-associative, way-shutdown, way-concatenating, and...

IATAC: a smart predictor to turn-off L2 cache lines
Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle
Pages: 55-77
DOI: 10.1145/1061267.1061271
As technology evolves, power dissipation increases and cooling systems become more complex and expensive. There are two main sources of power dissipation in a processor: dynamic power and leakage. Dynamic power has been the most significant factor,...

Accelerated warmup for sampled microarchitecture simulation
John W. Haskins, Jr., Kevin Skadron
Pages: 78-108
DOI: 10.1145/1061267.1061272
To reduce the cost of cycle-accurate software simulation of microarchitectures, many researchers use statistical sampling: by simulating only a small, representative subset of the end-to-end dynamic instruction stream in cycle-accurate detail,...