Architecture and Code Optimization (TACO)


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ACM Transactions on Architecture and Code Optimization (TACO), Volume 1 Issue 4, December 2004

The optimum pipeline depth considering both power and performance
A. Hartstein, Thomas R. Puzak
Pages: 369-388
DOI: 10.1145/1044823.1044824
The impact of pipeline length on both the power and performance of a microprocessor is explored both by theory and by simulation. A theory is presented for a range of power/performance metrics, BIPSm/W. The theory shows that the...

Toward kilo-instruction processors
Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez
Pages: 389-417
DOI: 10.1145/1044823.1044825
The continuously increasing gap between processor and memory speeds is a serious limitation to the performance achievable by future microprocessors. Currently, processors tolerate long-latency memory operations largely by maintaining a high number of...

An analysis of a resource efficient checkpoint architecture
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan
Pages: 418-444
DOI: 10.1145/1044823.1044826
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically required to buffer and process such instruction window sizes significantly...

Tolerating memory latency through push prefetching for pointer-intensive applications
Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee
Pages: 445-475
DOI: 10.1145/1044823.1044827
Prefetching is often used to overlap memory latency with computation for array-based applications. However, prefetching for pointer-intensive applications remains a challenge because of the irregular memory access pattern and pointer-chasing problem....