ACM DL

Architecture and Code Optimization (TACO)

Menu

Search Issue
enter search term and/or author name

Archive


ACM Transactions on Architecture and Code Optimization (TACO), Volume 13 Issue 3, September 2016

Variable Liberalization
Sanyam Mehta, Pen-Chung Yew
Article No.: 23
DOI: 10.1145/2963101

In the wake of the current trend of increasing the number of cores on a chip, compiler optimizations for improving the memory performance have assumed increased importance. Loop fusion is one such key optimization that can alleviate memory...

RATT-ECC: Rate Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memory
Hsing-Min Chen, Carole-Jean Wu, Trevor Mudge, Chaitali Chakrabarti
Article No.: 24
DOI: 10.1145/2957758

This article proposes a rate-adaptive, two-tiered error-correction scheme (RATT-ECC) that provides strong reliability (1010x reduction in raw FIT rate) for an HBM-like 3D DRAM system. The tier-1 code is a strong symbol-based code...

Implementing Dense Optical Flow Computation on a Heterogeneous FPGA SoC in C
Wenjie Chen, Zhibin Wang, Qin Wu, Jiuzhen Liang, Zhilei Chai
Article No.: 25
DOI: 10.1145/2948976

High-quality optical flow computation algorithms are computationally intensive. The low computational speed of such algorithms causes difficulties for real-world applications. In this article, we propose an optimized implementation of the...

Optimization Models for Three On-Chip Network Problems
Nilay Vaish, Michael C. Ferris, David A. Wood
Article No.: 26
DOI: 10.1145/2943781

We model three on-chip network design problems—memory controller placement, resource allocation in heterogeneous on-chip networks, and their combination—as mathematical optimization problems. We model the first two problems as mixed...

Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache
Somayeh Sardashti, Andre Seznec, David A. Wood
Article No.: 27
DOI: 10.1145/2976740

Cache memories play a critical role in bridging the latency, bandwidth, and energy gaps between cores and off-chip memory. However, caches frequently consume a significant fraction of a multicore chip's area and thus account for a significant...

Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures
Eduardo H. M. Cruz, Matthias Diener, Laércio L. Pilla, Philippe O. A. Navaux
Article No.: 28
DOI: 10.1145/2975587

The performance and energy efficiency of modern architectures depend on memory locality, which can be improved by thread and data mappings considering the memory access behavior of parallel applications. In this article, we propose intense pages...

Maximizing Heterogeneous Processor Performance Under Power Constraints
Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout
Article No.: 29
DOI: 10.1145/2976739

Heterogeneous processors (e.g., ARM’s big.LITTLE) improve performance in power-constrained environments by executing applications on the ‘little’ low-power core and move them to the ‘big’ high-performance core when...

An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation
Bagus Wibowo, Abhinav Agrawal, Thomas Stanton, James Tuck
Article No.: 30
DOI: 10.1145/2975588

Processor soft-error rates are projected to increase as feature sizes scale down, necessitating the adoption of reliability-enhancing techniques, but power and performance overhead remain a concern of such techniques. Dynamic cross-layer...

List of Distinguished Reviewers ACM TACO 2014
Manuel Acacio
Article No.: 31
DOI: 10.1145/2989990