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Limit studies on Dynamic Voltage and Frequency Scaling (DVFS) provide apparently contradictory conclusions. On the one hand early limit studies report that DVFS is effective at large timescales (on the order of million(s) of cycles) with large...
Exploring the effects of on-chip thermal variation on high-performance multicore architectures
Chen-Yong Cher, Eren Kursun
Article No.: 2
Inherent temperature variation among cores in a multicore architecture can be caused by a number of factors including process variation, cooling and packaging imperfections, and even placement of the chip in the module. Current dynamic thermal...
Adaptive timekeeping replacement: Fine-grained capacity management for shared CMP caches
Carole-Jean Wu, Margaret Martonosi
Article No.: 3
In chip multiprocessors (CMPs), several high-performance cores typically compete for capacity in a shared last-level cache. This causes degraded and unpredictable memory performance for multiprogrammed and parallel workloads. In response, recent...
Deterministic finite automata characterization and optimization for scalable pattern matching
Lucas Vespa, Ning Weng
Article No.: 4
Memory-based Deterministic Finite Automata (DFA) are ideal for pattern matching in network intrusion detection systems due to their deterministic performance and ease of update of new patterns, however severe DFA memory requirements make it...
Parallelization libraries: Characterizing and reducing overheads
Abhishek Bhattacharjee, Gilberto Contreras, Margaret Martonosi
Article No.: 5
Creating efficient, scalable dynamic parallel runtime systems for chip multiprocessors (CMPs) requires understanding the overheads that manifest at high core counts and small task sizes.
In this article, we assess these overheads on Intel's...