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ACM Transactions on Architecture and Code Optimization (TACO), Volume 5 Issue 4, March 2009

Making secure processors OS- and performance-friendly
Siddhartha Chhabra, Brian Rogers, Yan Solihin, Milos Prvulovic
Article No.: 16
DOI: 10.1145/1498690.1498691

In today's digital world, computer security issues have become increasingly important. In particular, researchers have proposed designs for secure processors that utilize hardware-based memory encryption and integrity verification to protect the...

Generalizing neural branch prediction
Daniel A. Jiménez
Article No.: 17
DOI: 10.1145/1498690.1498692

Improved branch prediction accuracy is essential to sustaining instruction throughput with today's deep pipelines. Traditional branch predictors exploit correlations between pattern history and branch outcome to predict branches, but there is a...

Abstracting access patterns of dynamic memory using regular expressions
Jinseong Jeon, Keoncheol Shin, Hwansoo Han
Article No.: 18
DOI: 10.1145/1498690.1498693

Unless the speed gap between CPU and memory disappears, efficient memory usage remains a decisive factor for performance. To optimize data usage of programs in the presence of the memory hierarchy, we are particularly interested in two compiler...

Optimal trace scheduling using enumeration
Ghassan Shobaki, Kent Wilken, Mark Heffernan
Article No.: 19
DOI: 10.1145/1498690.1498694

This article presents the first optimal algorithm for trace scheduling. The trace is a global scheduling region used by compilers to exploit instruction-level parallelism across basic block boundaries. Several heuristic techniques have been...