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ACM Transactions on Architecture and Code Optimization (TACO), Volume 2 Issue 3, September 2005

Exploring the limits of leakage power reduction in caches
Yan Meng, Timothy Sherwood, Ryan Kastner
Pages: 221-246
DOI: 10.1145/1089008.1089009
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption. Caches, because of the fact that they account for the largest fraction of on-chip transistors in most modern processors,...

Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
Pages: 247-279
DOI: 10.1145/1089008.1089010
Thread-Level Speculation (TLS) provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or speculative memory state that needs to be separately buffered...

Merging path and gshare indexing in perceptron branch prediction
David Tarjan, Kevin Skadron
Pages: 280-300
DOI: 10.1145/1089008.1089011
We introduce the hashed perceptron predictor, which merges the concepts behind the gshare, path-based and perceptron branch predictors. This predictor can achieve superior accuracy to a path-based and a global perceptron predictor, previously...

Whole execution traces and their applications
Xiangyu Zhang, Rajiv Gupta
Pages: 301-334
DOI: 10.1145/1089008.1089012
Different types of program profiles (control flow, value, address, and dependence) have been collected and extensively studied by researchers to identify program characteristics that can then be exploited to develop more effective compilers and...