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Efficient and flexible architectural support for dynamic monitoring
Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, Josep Torrellas
Recent impressive performance improvements in computer architecture have not led to significant gains in the case of debugging. Software debugging often relies on inserting run-time software checks. In many cases, however, it is hard to find the root...
A way-halting cache for low-energy high-performance systems
Chuanjun Zhang, Frank Vahid, Jun Yang, Walid Najjar
Caches contribute to much of a microprocessor system's power and energy consumption. Numerous new cache architectures, such as phased, pseudo-set-associative, way predicting, reactive-associative, way-shutdown, way-concatenating, and...
IATAC: a smart predictor to turn-off L2 cache lines
Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle
As technology evolves, power dissipation increases and cooling systems become more complex and expensive. There are two main sources of power dissipation in a processor: dynamic power and leakage. Dynamic power has been the most significant factor,...
Accelerated warmup for sampled microarchitecture simulation
John W. Haskins, Jr., Kevin Skadron
To reduce the cost of cycle-accurate software simulation of microarchitectures, many researchers use statistical sampling: by simulating only a small, representative subset of the end-to-end dynamic instruction stream in cycle-accurate detail,...