ACM Transactions on

Architecture and Code Optimization (TACO)

Latest Articles

Reuse Distance-Based Probabilistic Cache Replacement

This article proposes Probabilistic Replacement Policy (PRP), a novel replacement policy that evicts the line with minimum estimated hit probability... (more)


We introduce MINIME-GPU, a novel automated benchmark synthesis framework for graphics processing units (GPUs) that serves to speed up architectural simulation of modern GPU architectures. Our framework captures important characteristics of original GPU applications and generates synthetic GPU benchmarks using the Open Computing Language (OpenCL)... (more)

Scalable Energy Efficiency with Resilience for High Performance Computing Systems

Ever-growing performance of supercomputers nowadays brings demanding requirements of energy efficiency and resilience, due to rapidly expanding size... (more)


Schedulers used by modern OSs (e.g., Oracle Solaris 11™ and GNU/Linux) balance load by balancing the number of threads in run queues of different cores. While this approach is effective for a single CPU multicore system, we show that it can lead to a significant load imbalance across CPUs of a multi-CPU multicore system. Because different... (more)

Four Metrics to Evaluate Heterogeneous Multicores

Semiconductor device scaling has made single-ISA heterogeneous processors a reality. Heterogeneous processors contain a number of different CPU cores... (more)


Phase Change Memory (PCM) devices are one of the known promising technologies to take the place of DRAM devices with the aim of overcoming the obstacles of reducing feature size and stopping ever growing amounts of leakage power. In exchange for providing high capacity, high density, and nonvolatility, PCM Multilevel Cells (MLCs) impose high write... (more)

Two-Level Hybrid Sampled Simulation of Multithreaded Applications

Sampled microarchitectural simulation of single-threaded applications is mature technology for over a decade now. Sampling multithreaded applications,... (more)

Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels

The addition of express channels to a traditional mesh network-on-chip (NoC) has emerged as a viable... (more)

Managing Mismatches in Voltage Stacking with CoreUnfolding

Five percent to 25% of power could be wasted before it is delivered to the computational resources on a die, due to inefficiencies of voltage... (more)


About TACO

The ACM Transactions on Architecture and Code Optimization focuses on hardware, software, and systems research spanning the fields of computer architecture and code optimization. Articles that appear in TACO present new techniques and concepts or report on experiences and experiments with actual systems. Insights useful to computer architects, hardware or software developers, system designers and tool builders are emphasized.

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Forthcoming Articles

A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution

We explore the interaction between the Hardware TM paradigm and Networks-On-Chip. We identify a huge source of superfluous network traffic due to failed requests in transaction conflicts. This problem adversely affects network performance and energy efficiency. As observed in a wide spectrum of workloads, 58% of the transactional network traffic is futile due to conflicts. To combat this problem, a novel in-network filtering mechanism is proposed. Experimental results show that our design reduces total network traffic by 21% for a set of high-contention benchmarks, thereby reducing energy consumption by 24%. These improvements are achieved with only 5% area overhead.

RFVP: Rollback-Free Value Prediction with Safe-to-Approximate Loads

This paper aims to tackle two fundamental memory bottlenecks: limited off-chip bandwidth (bandwidth wall) and long access latency (memory wall). To achieve this goal, our approach exploits the inherent error resilience of a wide range of applications. We introduce an approximation technique, called Rollback-Free Value Prediction (RFVP). When a certain safe-to-approximate load operations miss in the cache, RFVP predicts the requested values. However, RFVP never checks for or recovers from load value mispredictions, hence avoiding ...

FluidCheck: A Redundant Threading based Approach for Reliable Execution in Manycore Processors

In this paper, we present a mechanism to dynamically use the resources of SMT cores for checking the results of other threads, and a variety of heuristics for migration of such checker threads across cores. Secondly, to make the process of checking more efficient, we propose a set of architectural enhancements that reduce power consumption, decrease the length of the critical path, and reduce the load on the NoC. We design a 16 core system for running SPEC2006 based bag-of-tasks applications. We demonstrate that fully reliable execution can be attained with a mere 27% slowdown (42% better than traditional techniques).

FaultSim: A Fast Configurable Memory-Resilience Simulator for Conventional and 3D-Stacked Memory Systems

To architect future systems and to use emerging technology, system designers will need to employ strong error correction and repair techniques. Unfortunately, evaluating the relative effectiveness of these reliability mechanisms is often difficult and is traditionally done with analytical models, which are both error prone and time consuming to develop. To this end, this paper proposes FaultSim, a fast configurable memory-reliability simulation tool for 2D and 3D-stacked memory systems. FaultSim employs Monte Carlo simulations which are driven by real-world failure statistics. We discuss the novel algorithms and data structures used in FaultSim to accelerate the evaluation of different resilience schemes.

Iteration Interleaving based SIMD Lane Partition

The efficacy of single instruction, multiple data (SIMD) architectures is limited when handling divergent control flows. This circumstance results in SIMD fragments that use only a subset of the available lanes. In this paper, we propose an Iteration Interleaving based SIMD Lane Partition (IISLP) architecture that interleaves the execution of consecutive vector-iterations, and dynamically partitions SIMD lanes into branch-paths with comparable length. The benefits are twofold: SIMD fragments under divergent branches can execute in parallel, and the pathology of fragment starvation can also be well eliminated. Our experiments show that IISLP provides a speedup of 28% versus instruction shuffle.

Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures

Stacked memory designs are susceptible to newer failure modes that can cause large portions of memory, such as a bank, to become faulty. To avoid data loss from large-granularity failures, the memory system may use symbol-based codes that stripe the data for a cache line across several banks (or channels). Unfortunately, such data-striping reduces memory level parallelism causing significant slowdown and higher power consumption. This paper proposes Citadel, a robust memory architecture that allows the memory system to retain each cache line within one bank, thus allowing high performance, lower power and efficiently protects the stacked memory from large-granularity failures.

Enabling PGAS Productivity with Hardware Support for Shared Address Mapping; a UPC Case Study

The PGAS programming model strikes a balance between the locality-aware message-passing model and the easy-to-use shared memory model. However, the rich memory model comes at a performance cost which forces users to hand optimize their code to achieve full performance. We present a new hardware alongside a prototype compiler allowing to efficiently handle PGAS and creating a productive environment. Two implementations of the system are realized: thru full system simulation and FPGA prototyping, allowing to evaluate performance and hardware cost. Results show improvement ranging from 1.2x to 8x on non hand-optimized codes.

Symmetry-agnostic Coordinated Management of the Memory Hierarchy in Multi-core Systems

The last-level cache (LLC) and memory bandwidth are two important shared resources in multi-core systems. Coordinated management of these resources leads to good performance. DRAM is still the technology of choice, but faces energy, reliability and scalability challenges. Non-volatile memories are gaining traction as DRAM replacement candidates. While DRAM is read/write symmetric, many non-volatile memory technologies experience read/write asymmetry: writes are much slower and more power hungry than reads. Whether the memory is symmetric or asymmetric influences the way of managing shared resources. We propose symmetry-agnostic schemes to mange shared LLC and memory bandwidth, benefiting both symmetric and asymmetric memory.

DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators

SoCs integrate CPU cores and Hardware Accelerators (HWAs) that share the main memory, causing interference among memory requests. The result is missed deadlines for HWAs and low CPU performance. We propose a Deadline-Aware memory Scheduler for Heterogeneous systems (DASH), that overcomes the problems using three ideas. First, DASH prioritizes a HWA any time when it is not on track to meet its deadline. Second, DASH prioritizes HWAs over memory-intensive CPU applications which are not latency sensitive. Third, DASH prioritizes short-deadline HWAs based on worst-case memory access time estimates. DASH significantly improves CPU performance while always meeting the deadlines for HWAs.

Resistive GP-SIMD Processing-In-Memory

GP-SIMD, a hybrid general purpose SIMD architecture, addresses the challenge of data synchronization by in-memory computing, through combining data storage and massive parallel processing. In resistive GP-SIMD, a resistive row and column addressable crossbar is utilized, replacing the modified CMOS SRAM storage previously proposed for GP-SIMD architecture. The use of resistive memory technology allows scaling the GP-SIMD from few millions to few hundred millions of processing units. The performance, power consumption and power efficiency of a resistive GP-SIMD are compared with the CMOS version. A framework for in-place arithmetic operation on a single multi-valued resistive cell is explored.

Fence Placement for Legacy Data-Race-Free Programs via Synchronization Read Detection

Shared-memory programmers traditionally assumed Sequential Consistency (SC), but modern systems have relaxed memory consistency. Here, the trend in languages is towards Data-Race-Free (DRF) models, where, assuming annotated synchronizations and the program being well-synchronized by those synchronizations, the hardware and compiler guarantee correctness. However, legacy programs lack annotations, so even well-synchronized (legacy DRF) programs aren't recognized. For legacy DRF programs, we can significantly prune the set of memory orderings determined by automated fence placement, by automatically identifying synchronization reads. We prove our rules for identifying them conservative, implement them within LLVM, and observe a 30% average performance improvement over previous techniques.

Sensible Energy Accounting with Abstract Metering for Multicore Systems

Energy is arguably the most expensive resource in current computing systems. Standard metering approaches are not capable of delivering consistent results with shared resources. Accurately quantifying energy in multi-core environment presents a challenge but also an opportunity for optimization. This paper introduces Sensible Energy Accounting(SEA). For a task running in a multicore system, SEA accurately estimates the energy the task would have consumed running in isolation with a given fraction of the CMP shared resources. We explain the potential benefits of SEA in different domains and describe hardware techniques to implement for shared caches and on-core resources in SMT processors.

Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface

Limited memory bandwidth is a critical bottleneck in modern systems. 3D-stacked DRAM enables higher bandwidth by leveraging wider Through-Silicon-Via channels, but todays systems cannot fully exploit them due to the limited internal bandwidth of DRAM. Our goal is to enable higher bandwidth in 3D-stacked DRAM without the increased cost of adding more in-DRAM interfaces. We instead exploit otherwise-idle resources, such as in-DRAM interfaces, already existing within the multiple DRAM layers by accessing them simultaneously. Our architecture, Simultaneous Multi Layer Access, provides higher bandwidth by aggregating the internal bandwidth of multiple layers and transferring the available data at higher IO frequency.

Integer Linear Programming Based Scheduling for Transport Triggered Architectures

Static machines such as VLIW architectures move complexity from the hardware to the compiler. Transport triggered architectures (TTA) take the compiler-oriented philosophy even further. The main benefit of this is the reduced register file pressure, with a drawback of adding even more complexity to the compiler side. In this article, we propose an Integer Linear Programming based instruction scheduling model for TTAs. In addition to producing shorter schedules, the number of register accesses in the compiled programs is generally notably less than those with a heuristic scheduler.

A Framework for Application Guided Task Management on Heterogeneous Embedded Systems

In this paper, we propose a framework for energy-aware task management in heterogeneous embedded platforms, which integrates a set of novel application-aware management mechanisms for efficient resource utilization, frequency scaling and task migration. These mechanisms rely on a new management concept, which promotes performance fairness among running tasks to attain energy savings, while respecting the target performance of parallel applications. The proposed framework integrates several components for accurate run-time monitoring and application self-reporting. Experimental results show that energy savings of up to 39% were achieved in a state-of-the-art embedded platform for a set of real-world SPEC CPU2006 and PARSEC benchmarks.

Optimizing Control Transfer and Memory Virtualization in Full System Emulators

This paper focuses on optimizing the performance of full system emulators. First, we optimize performance by enabling classic control transfer optimizations of dynamic binary translation in full system emulation, such as indirect branch target caching and block chaining. Second, we improve the performance of memory virtualization of cross-ISA virtual machines by improving efficiency of software TLB. We implement our optimizations on QEMU, an industrial-strength full system emulator, along with the Android emulator. Experimental results show that our optimizations achieve an average speedup of 1.92X for ARM-to-X86-64 QEMU running SPEC CINT2006 benchmarks with reference inputs and 1.42X for Android ARM emulator.

JavaScript Parallelizing Compiler for Exploiting Parallelism from Data-Parallel HTML5 Applications

In the advent of the HTML5 standard, JavaScript has been expected to undertake an unprecedented level of increasing computational workload. In this article, we propose an automatic JavaScript parallelizing compiler, leveraging affine loop analysis of a conventional static compiler. Also, we propose a mechanism for safely handling the failure at a low cost, based on compiler techniques and idempotence property. The experimental results show average speedups of 2.07 and 3.02 in Polybench Suite and Pixastic Library on a quad core platform.

Rethinking Memory Permissions for Protection Against Cross-Layer Attacks

The inclusive permissions structure of modern commodity CPUs provides privileged system software layers with arbitrary permissions to access and modify client processes, allowing them to manage these clients and the system resources efficiently. Unfortunately, these inclusive permissions allow a compromised high-privileged software layer to perform arbitrary malicious activities. In this paper, our goal is to prevent attacks that cross system layers while maintaining the abilities of system software to manage the system. In particular, we present a hardware-supported page permission framework for physical pages that is based on the concept of non-inclusive sets of memory permissions.

A Compile-Time Optimization Method for WCET Reduction in Real-Time Embedded Systems through Block Formation

Compile-time optimizations usually are designed to reduce average-case execution time (ACET). While ACET is a main concern in high-performance computing systems, in real-time embedded systems, worst-case execution time (WCET) is much more important. In this paper, we propose a compile-time method for WCET reduction in real-time embedded systems. In the proposed method, based on the predicated execution capability of embedded processors, code blocks that are in the worst-case paths of the program are merged to increase opportunity for WCET reduction. The experimental results show that the proposed method can reduce WCET by up to 21% compared to the similar methods.

Adaptive Correction of Sampling Bias in Dynamic Call Graphs

This article introduces a novel low-overhead adaptive technique of correcting sampling bias in profiling dynamic call graphs. Timer-based sampling keeps the overhead low but sampling bias lowers the accuracy when either observable call events or sampling actions are not equally spaced in time. To mitigate sampling bias, our adaptive correction technique weights each sample by monitoring time-varying spacing of call events and sampling actions. We implemented and evaluated our adaptive correction technique in Jikes RVM, a high-performance virtual machine. In our empirical evaluation, our technique significantly improved the sampling accuracy without measurable overhead and resulted in effective feedback directed inlining.

A Methodology Addressing the Compiler Optimization Phase-Ordering Problem by exploiting the hardware architecture parameters

The Polyhedral Model of Non-Linear Loops

Apollo is a framework that applies the polytope model dynamically by using TLS. Apollo can predict, at runtime, whether the codes are behaving linearly or not, and applies polyhedral transformations on-the-fly. This paper presents a novel system which enables Apollo to handle codes whose memory accesses and loop bounds are not necessarily linear. More generally, this approach expands the applicability of the polytope model to a wider class of codes. Plugging together both linear and non linear accesses to the dependence prediction model enables the application of polyhedral loop optimizing transformations even for non linear code kernels.

Falcon: A Graph Manipulation Language for Heterogeneous Systems

Graph algorithms are used in several domains and they possess large amounts of parallelism. Unfortunately, tuning their implementation for efficient execution on a particular hardware is challenging, time-consuming, and error-prone. Further, efficient execution on different kinds of hardware requires modifying the low-level codes separately for each platform. To address these issues, we propose a Domain Specific Language, Falcon, for implementing graph algorithms that (abstracts the hardware, provides constructs to write explicitly parallel programs at a higher level, and can work with morph algorithms. We illustrate that the generated code is close to hand-tuned implementations in performance.

ParsecSs: Evaluating the Impact of Task Parallelism in the Parsec Benchmark Suite.

In this work we show how parallel applications can be efficiently implemented using asynchronous tasks and dataflow relations. We also evaluate the benefits of such parallel paradigms with respect to other approaches. We use the PARSEC benchmark suite as our test bed, which includes applications representative of a widerange of domains from HPC to desktop and server applications. We adopt different parallelization techniques, tailored to the needs of each application, in order to fully exploit thetask-based model. Our evaluation shows that task parallelism can achieve better performance and more maintainable and portable code than conventional parallelization models, such as Pthreads.

On how to Accelerate Iterative Stencil Loops: A Scalable Streaming-based Approach

Stencil computations appear in a variety of different fields of application. Their computationally intensive nature requires optimized implementations, for both generic and custom processors. This work introduces a methodology to systematically design power efficient hardware accelerators for the optimal execution of Iterative Stencil Loops on FPGAs. As part of the methodology we introduce a streaming-based architecture with both low resource usage and optimal data reuse factor; and we introduce a technique capable to deliver a quasi-linear execution time speedup with constant bandwidth. Results show large improvements in speedup and demonstrate a quasi-linear scaling, while consuming constant off-chip bandwidth.

Automatic Vectorization of Interleaved Data Revisited

Automatically exploiting multimedia instruction sets (SSE, AVX, NEON) is a critically important task for optimizing compilers. An existing approach used by GCC gen- erates extremely efficient code for loops with power-of-two interleaving factors (strides). In this paper we pro- pose a generalization of this approach for any compile-time constant interleaving factor. In addition, we propose several novel program transformations made possible by our gen- eralized representation of the problem. Our vectorization approach results in a mean speedup of 1.77x over scalar code in real-world benchmarking on a selection of BLAS Level 1 routines, versus 1.43x improvement attained by GCC.


Publication Years 2004-2015
Publication Count 424
Citation Count 1306
Available for Download 424
Downloads (6 weeks) 2748
Downloads (12 Months) 28628
Downloads (cumulative) 169988
Average downloads per article 401
Average citations per article 3
First Name Last Name Award
Sarita Adve ACM Fellows (2010)
Iris Bahar ACM Distinguished Member (2012)
Laxmi N Bhuyan ACM Fellows (2000)
Douglas C Burger ACM Fellows (2010)
ACM Distinguished Member (2008)
ACM Senior Member (2006)
Martin Burtscher ACM Distinguished Member (2014)
ACM Senior Member (2006)
John B Carter ACM Senior Member (2015)
Jason Cong ACM Fellows (2008)
William J Dally ACM - IEEE CS Eckert-Mauchly Award (2010)
ACM Fellows (2002)
Jack Davidson ACM Fellows (2008)
Bronis R. De Supinski ACM Gordon Bell Prize (2006)
Michel Dubois ACM Fellows (2005)
Nikil D. Dutt ACM Fellows (2014)
ACM Distinguished Member (2007)
Joel Emer ACM - IEEE CS Eckert-Mauchly Award (2009)
ACM Fellows (2004)
Michael Franz ACM Distinguished Member (2006)
Guang Gao ACM Fellows (2007)
Phillip B Gibbons ACM Fellows (2006)
Rajiv Gupta ACM Fellows (2009)
Mary W Hall ACM Distinguished Member (2010)
Tim Harris ACM Senior Member (2007)
Mark Hill ACM Fellows (2004)
Mark A Horowitz ACM Fellows (2003)
Mary Jane Irwin ACM-W Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
ACM Fellows (1996)
Norman Jouppi ACM - IEEE CS Eckert-Mauchly Award (2015)
ACM Fellows (2006)
David R Kaeli ACM Distinguished Member (2014)
Stephen Keckler ACM Fellows (2011)
ACM Senior Member (2006)
ACM Grace Murray Hopper Award (2003)
Nectarios G. Koziris ACM Senior Member (2009)
Sharad Malik ACM Fellows (2014)
Margaret Martonosi ACM Fellows (2009)
Sally A McKee ACM Senior Member (2013)
Shubu Mukherjee ACM Fellows (2011)
ACM Distinguished Member (2009)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Vijaykrishnan Narayanan ACM Fellows (2014)
David Padua ACM Fellows (2007)
Milos Prvulovic ACM Senior Member (2009)
Lawrence Rauchwerger ACM Distinguished Member (2014)
Vivek Sarkar ACM Fellows (2008)
ACM Distinguished Member (2006)
Robert Schreiber ACM Fellows (2012)
ACM Distinguished Member (2006)
Martin Schulz ACM Gordon Bell Prize (2006)
Kevin Skadron ACM Distinguished Member (2010)
ACM Senior Member (2007)
Mary Lou Soffa ACM - IEEE CS Ken Kennedy Award (2012)
ACM Fellows (1999)
J. Gregory Steffan ACM Senior Member (2009)
Per O Stenstrom ACM Fellows (2008)
Subhash Suri ACM Fellows (2010)
ACM Distinguished Member (2007)
Josep Torrellas ACM Fellows (2010)
Dean M Tullsen ACM Fellows (2011)
Mateo Valero ACM Distinguished Service Award (2012)
ACM - IEEE CS Eckert-Mauchly Award (2007)
ACM Fellows (2002)
Hans Vandierendonck ACM Senior Member (2013)
Stamatis Vassiliadis ACM Fellows (2004)
Richard W. Vuduc ACM Gordon Bell Prize (2010)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Andreas Zeller ACM Fellows (2010)
Lixia Zhang ACM Fellows (2006)
Yuanyuan Zhou ACM Fellows (2013)
ACM Distinguished Member (2011)
Yuanyuan Zhou ACM Fellows (2013)
ACM Distinguished Member (2011)

First Name Last Name Paper Counts
Lieven Eeckhout 16
André Seznec 8
Rajiv Gupta 8
Yuan Xie 8
Kevin Skadron 7
Stijn Eyerman 7
Bruce Childers 6
Michael O'Boyle 6
Antonia Zhai 6
Margaret Martonosi 6
Norman Jouppi 6
Yan Solihin 5
Pen Yew 5
Haitham Akkary 5
Shlomo Weiss 5
Jun Yang 5
Weichung Hsu 5
Timothy Sherwood 5
Christian Wimmer 5
Laxmi Bhuyan 5
Jingling Xue 5
David Whalley 5
David Gregg 5
Antonio González 5
Adrián Cristal 5
Tor Aamodt 4
Jack Davidson 4
Oğuz Ergin 4
Louis Pouchet 4
Milos Prvulovic 4
Henk Corporaal 4
Sarita Adve 4
Mateo Valero 4
Osman Ünsal 4
Chengyong Wu 4
Christos Kozyrakis 4
Timothy Jones 4
Jaume Abella 4
David Brooks 4
Mateo Valero 4
Chialin Yang 3
Shuangde Fang 3
Walid Najjar 3
Ramón Doallo 3
Josep Torrellas 3
Ponnuswamy Sadayappan 3
José Llabería 3
Chandra Krintz 3
Youtao Zhang 3
Antoniu Pop 3
Daniel Jiménez 3
Avi Mendelson 3
Yiannakis Sazeides 3
Rubén Titos-Gil 3
José GarcíA 3
Mahmut Kandemir 3
Frank Mueller 3
Mary Soffa 3
James Tuck 3
Jue Wang 3
Michael Franz 3
Hanspeter Mössenböck 3
Prasad Kulkarni 3
Víctor Viñals 3
Xiangyu Dong 3
Francisco Cazorla 3
Kim Hazelwood 3
David Tarjan 3
María Garzarán 3
Yu Du 3
Pierre Michaud 3
Hans Vandierendonck 3
Francky Catthoor 3
Lizy John 3
Basilio Fraguela 3
Wengfai Wong 3
Paolo Ienne 3
Aamer Jaleel 3
Yunji Chen 3
Jose Renau 3
Michael Spear 3
Xiaofei Liao 2
Sebastian Hack 2
Betul Buyukkurt 2
Yuanjie Huang 2
Lishiuan Peh 2
José Martínez 2
Changhui Lin 2
Guyeon Wei 2
Jorge Albericio 2
Alex Jones 2
Olivier Temam 2
Michael Smith 2
Stefan Brunthaler 2
Ron Gabor 2
Jin Lin 2
Dean Tullsen 2
Zheng Wang 2
Ran Ginosar 2
Jagannathan Ramanujam 2
Neil Vachharajani 2
Bjorn De Sutter 2
Yunheung Paek 2
Rami Melhem 2
Wim Heirman 2
Ben Juurlink 2
Shashidhar Mysore 2
Magnus Själander 2
Christophe Dubach 2
Angeliki Kritikakou 2
Olivier Temam 2
Marcelo Cintra 2
Sanyam Mehta 2
Fabrice Rastello 2
Albert Cohen 2
Stefanos Kaxiras 2
Alex Ramírez 2
Jason Hiser 2
Jianjun Li 2
David August 2
Simon Steely 2
Daniel Mossé 2
Anurag Negi 2
Ramesh Karri 2
Chuntao Jiang 2
Gabriel Loh 2
Bronis De Supinski 2
Tinfook Ngai 2
Hwansoo Han 2
Scott Mahlke 2
Nathanael Premillieu 2
Wenjia Ruan 2
Venmugil Elango 2
Min Feng 2
Xuejun Yang 2
William Hasenplaugh 2
Alberto Ros 2
Sven Verdoolaege 2
Miquel Moretó 2
Uday Bondhugula 2
Quan Chen 2
Xiaobing Feng 2
John Kim 2
Michael O’Boyle 2
Grigori Fursin 2
Jacob Leverich 2
Karthik Sankaranarayanan 2
Frederic Chong 2
Glenn Reinman 2
Komal Jothi 2
Yuanyuan Zhou 2
Cedric Nugteren 2
Maximilien Breughe 2
Abhishek Bhattacharjee 2
Manlap Li 2
Joel Emer 2
Banit Agrawal 2
Yong Li 2
Doug Simon 2
Yang Chen 2
Mary Irwin 2
Joseph Sharkey 2
Todd Austin 2
Edwin Bonilla 2
Kishore Pusukuri 2
Amit Golander 2
Diego Andrade 2
Mageda Sharafeddine 2
Ravishankar Iyer 2
Li Zhao 2
Yangchun Luo 2
Gautham Beeraka 2
Mauricio Álvarez-Mesa 2
Bart Coppens 2
Miao Zhou 2
Pablo Ibáñez 2
Michela Becchi 2
Arun Kanuparthi 2
Yosi Asher 2
Rajkishore Barik 2
Yuanshin Hwang 2
Jason Loew 2
Costas Goutis 2
Per Larsen 2
Chuanjun Zhang 2
Todd Mowry 2
Oliverio Santana 2
Chenggang Wu 2
Jason Cong 2
Trevor Carlson 2
Jungho Ahn 2
Ghassan Shobaki 2
Dmitry Ponomarev 2
Xiangyu Dong 2
Vasilios Kelefouras 2
Roy Ju 2
Naveen Muralimanohar 2
Onur Mutlu 2
Guru Venkataramani 2
Ram Rangan 2
Ibrahim Hur 2
Erven Rohou 2
Karthikeyan Sankaralingam 2
Motohiro Kawahito 2
Zhibin Yu 2
Emilio Zapata 1
Venkata Tavva 1
Karine Heydemann 1
Subhash Suri 1
Shubhendu Mukherjee 1
Jun Yan 1
Tianshi Chen 1
Kent Wilken 1
Kishore Kumar Pusukuri 1
Pavlos Mattheakis 1
Konrad Trifunovic 1
Chunyue Liu 1
Gabe Rudy 1
Christian Fensch 1
Greg Stitt 1
Pieter Custers 1
Michele Tartara 1
Yohan Ko 1
Jonghee Youn 1
Rami Melhem 1
Mehmet Belviranli 1
Qingbo Wu 1
Richard Vuduc 1
Wes Masri 1
Srimat Chakradhar 1
Hans Graf 1
Chienchi Chen 1
Dyer Rolán 1
Cyriel Minkenberg 1
Yiran Chen 1
Bing Liu 1
Robert Seepers 1
Vesna Smiljkovic 1
George Tzenakis 1
Yujie Liu 1
Lingmei Weng 1
Yingwei Luo 1
Zhe Wang 1
Junli Gu 1
Hyunggyu Lee 1
Michael Andersch 1
Nikil Dutt 1
John Byrne 1
Laura Ramirez 1
Boryeh Shen 1
Wuu Yang 1
Miao Yu 1
Samuel Burri 1
Chunghsiang Lin 1
Atieh Lotfi 1
Abbas Rahimi 1
Gilles Duboscq 1
Tao Zhang 1
Ivan Stalev 1
Matt Poremba 1
Zhiying Wang 1
Etem Deniz 1
Lee Howes 1
Johannes Doerfert 1
Olivier Rochecouste 1
John Cortes 1
Mojtaba Mehrara 1
Hideho Arakida 1
Haiming Liu 1
Hugh Leather 1
Mingyu Chen 1
Licheng Chen 1
Gulfem Savrun-Yeniceri 1
Eric Seckler 1
Michal Wegiel 1
Weifeng Xu 1
Shyhtsunfelix Wu 1
Jedidiah Crandall 1
Shiwen Hu 1
Brett Brotherton 1
Lin Tan 1
Hussam Mousa 1
Salvador Petit 1
Bin Li 1
Dongrui Fan 1
Gabriel RodrÍguez 1
Juan Touriño 1
Cristóbal Camarero 1
Ramón Beivide 1
Zheng Zhang 1
Vivek Seshadri 1
Amnon Barak 1
Tal Ben-Nun 1
Magnus Jahre 1
J Ramanujam 1
Ananta Tiwari 1
Yujie Liu 1
Quentin Colombet 1
Florian Brandner 1
Pradip Valathol 1
Dongrui She 1
Paraskevas Evripidou 1
Efraim Rotem 1
David Padua 1
Patrick Eitschberger 1
Srikanth Srinivasan 1
Ryan Kastner 1
Kanad Ghose 1
Luis Ceze 1
David Kaeli 1
Xi Li 1
Junneng Zhang 1
Kiyoung Choi 1
Jian Li 1
Ram Rajamony 1
Nectarios Koziris 1
Jason Mars 1
YenMing Chen 1
Hyunjin Lee 1
Anil Krishna 1
Robert Bell 1
R Rakvic 1
Jeffery Von Ronne 1
Benoit Meister 1
Andreas Lankes 1
Andreas Herkersdorf 1
Valeria Bertacco 1
Gyungsu Byun 1
Glenn Reinman 1
Sabih Gerez 1
Zhenjiang Wang 1
Leonid Domnitser 1
Nael Abu-Ghazaleh 1
Manuel Acacio 1
Wolfgang Karl 1
Guang Gao 1
Tong Wu 1
Donghyuk Woo 1
Hsien Lee 1
Emrah Islek 1
Stefano Carlo 1
Davide Bertozzi 1
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Universidad de Murcia 11
Cornell University 11
University of Dublin, Trinity College 11
University of California, Los Angeles 11
Carnegie Mellon University 11
University of Minnesota Twin Cities 11
Florida State University 12
National Taiwan University 12
INRIA Institut National de Rechereche en Informatique et en Automatique 12
Universidad de Zaragoza 12
University Michigan Ann Arbor 12
University of Wisconsin Madison 12
Harvard University 13
Seoul National University 14
Institute of Computing Technology Chinese Academy of Sciences 14
IBM Research 15
American University of Beirut 15
HP Labs 16
Institut de Recherche en Informatique et Systemes Aleatoires 16
University of California, Irvine 17
Stanford University 17
University of Texas at Austin 17
Barcelona Supercomputing Center 17
Ohio State University 18
Georgia Institute of Technology 19
Shanghai Jiaotong University 19
National University of Defense Technology China 22
University of Edinburgh 24
University of California, Santa Barbara 24
North Carolina State University 25
Pennsylvania State University 26
Princeton University 26
University of Illinois at Urbana-Champaign 28
Chinese Academy of Sciences 35
University of Virginia 36
University of California, Riverside 37
University of Pittsburgh 39
Universitat Politecnica de Catalunya 44
Ghent University 46
Intel Corporation 56

ACM Transactions on Architecture and Code Optimization (TACO)

Volume 12 Issue 4, November 2015  Issue-in-Progress
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